1. Field of the Invention:
The present invention relates generally to the design and fabrication of circuit layouts, and more particularly to methods which account for clock skew during the design and fabrication of circuit layouts.
2. State of the Art:
Conventional methods for designing and fabricating circuit layouts, such as integrated circuits, often include techniques for determining, prior to fabrication, those paths which possess the longest combination of physical signal transmission delays from an input node to an output node (i.e., longest combinational delay). The path of the circuit layout having the longest combinational delay from a first storage element to a second storage element is typically referred to as the critical path.
Because the delay time associated with each element of a circuit layout is known in advance, a combinational delay along each path (e.g., from a clocking in of data via each clock input of a first storage element to a data input of a subsequent storage element) can be measured. The combinational delay for each path is typically referred to as a weight of the path. Weights for each path are subsequently compared, with the greatest weight being deemed the critical path. A critical delay representing a worst case delay between storage elements of the circuit layout defines the maximum frequency (e.g., clock frequency) at which the circuit layout can operate.
It is important to determine the maximum frequency at which a circuit layout can operate in order to avoid what are referred to as "race" conditions. A race condition occurs when a node or circuit component in the circuit layout processes (e.g., stores) data prior to receipt of all necessary inputs. For example, assume that a circuit layout is operated at a clock frequency greater than the maximum frequency specified for the critical path. Further, assume that the circuit layout includes a storage element, such as a flip-flop at an output node of the critical path. Because the frequency of the circuit layout exceeds the maximum permissible frequency given the critical path, it is likely that a clock input to the flip-flop will occur prior to receipt of data at a data input of the flip-flop. Accordingly, the flip-flop will be clocked with invalid data. This can cause significant operational error of the circuit layout and is simply intolerable in the industry.
One typical method for designing and fabricating circuit layouts is described in a document entitled "Efficient Algorithms For Extracting The K Most Critical Paths In Timing Analysis", Design Automation Conference, 1989, pages 649-653, by S. Yen, D. Du and S. Ghanta. The method disclosed in this document represents conventional techniques of circuit design and fabrication which assume that clock distribution for the circuit layout is perfectly balanced. That is, clock signals are presumed to arrive at all storage element clock pins at the same time (i.e., no clock skew). The critical path is therefore considered to be directly proportional to the longest combinational delay through the circuit layout between two storage elements.
While conventional methods for locating critical paths have worked relatively well in the design and fabrication of circuit layouts to date, such methods often result in the fabrication of circuit layouts which include timing errors as the speed of circuit layouts continues to increase in the industry. Because conventional techniques determine a critical path based on the longest combinational delay between two storage elements through a physical layout of the circuit, race conditions which exist in the circuit layout due to clock skew go undetected. These race conditions can result in serious operational malfunctions. Accordingly, it would be desirable to provide a method for designing and fabricating circuit layouts which can account for clock skew in determining critical paths through a circuit layout.